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stk14c88-5 256 kbit (32k x 8) autostore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-51038 rev. ** revised march 02, 2009 features 35 ns and 45 ns access times hands off automatic store on power down with external 68 f capacitor store to quantumtrap? nonvolatile elements is initiated by software, hardware, or autostore? on power down recall to sram initiated by software or power up unlimited read, write, and recall cycles 1,000,000 store cycl es to quantumtrap 100 year data retention to quantumtrap single 5v+ 10% operation military temperature 32-pin (300 mil) cdip and lcc (450 mil) packages functional description the cypress stk14c88-5 is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles , while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. a hardware store is initiated with the hsb pin. store/ recall control power control software detect static ram array 512 x 512 quantum trap 512 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 13 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 11 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 logic block diagram [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 2 of 17 pin configurations pin definitions pin name alt io type description a 0 ?a 14 input address inputs . used to select one of the 32,768 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data io lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the io pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . hsb input or output hardware store busy (hsb ) . when low, this output indicates a hardware store is in progress. when pulled low external to the chip, it initiate s a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. figure 1. pin diagram: 32-pin dip figure 2. pin diagram: 32-pin lcc [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 3 of 17 device operation the stk14c88-5 nvsram is made up of two functional compo- nents paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation) or from the nonvolatile cell to sram (the recall operation). this unique arch itecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram read and write operations are inhibited. the stk14c88-5 supports unlimit ed reads and writes similar to a typical sram. in addition, it provides unlimited recall opera- tions from the nonvolatile cells and up to one million store operations. sram read the stk14c88-5 performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?14 determines the 32,768 data bytes accessed. when the read is initiated by an ad dress transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must rema in stable until either ce or we goes high at the en d of the cycle. the data on the common io pins dq 0?7 are written into the me mory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the stk14c88-5 stores data to nvsram using one of three storage operations: 1. hardware store activated by hsb 2. software store activated by an address sequence 3. autostore on device power down autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the stk14c88-5. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 3 shows the proper connectio n of the storage capacitor (v cap ) for automatic store operation. a charge storage capacitor having a capacitor of between 68uf and 220uf (+ 20%) rated at 6v should be provided. the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up is placed on we to hold it inactive during power up. in system power mode, both v cc and v cap are connected to the +5v power supply without the 68 f capacitor. in this mode, the autostore function of the stk1 4c88-5 operates on the stored system charge as power goes do wn. the user must, however, guarantee that v cc does not drop below 3.6v during the 10 ms store cycle. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored, unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. an optional pull-up resist or is shown connected to hsb . the hsb signal is monitored by th e system to detect if an autostore cycle is in progress. if the power supply drops faster than 20 us/volt before vcc reaches v switch , then a 2.2 ohm resistor should be connected between v cc and the system supply to avoid momentary excess of current between v cc and v cap . autostore inhibit mode if an automatic store on power loss is not required, then v cc is tied to ground and + 5v is applied to v cap ( figure 4 ). this is the autostore inhibit mode, wh ere the autostore function is disabled. if the stk14c88-5 is operated in this configuration, references to v cc are changed to v cap throughout this data sheet. in this mode, store operations are triggered through software control or the hsb pin. to enable or disable autostore using an i/o port pin see ?? on page 5 . it is not permissible to change between these three options? on the fly?. figure 3. autostore mode [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 4 of 17 hardware store (hsb ) operation the stk14c88-5 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware stor e cycle. when the hsb pin is driven low, the stk14c88-5 conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram takes place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition, while the store (initiated by any means) is in progress. pull up this pin with an external 10k ohm resistor to v cap if hsb is used as a driver. sram read and write operations, that are in progress when hsb is driven low by any means, are given time to complete before the store operation is initiated. after hsb goes low, the stk14c88-5 continues sram operations for t delay . during t delay , multiple sram read operations take place. if a write is in progress when hsb is pulled low, it allows a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. during any store operation, rega rdless of how it is initiated, the stk14c88-5 continues to drive the hsb pin low, releasing it only when the store is complete. after completing the store operation, the stk14c88-5 remains disabled until the hsb pin returns high. if hsb is not used, it is left unconnected. hardware recall (power up) during power up or after any low power condition (v cc < v reset ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. if the stk14c88-5 is in a write state at the end of power up recall, the sram data is corrupted. to help avoid this situation, a 10 kohm resistor is connected either between we and system v cc or between ce and system v cc . software store data is transferred from the sr am to the nonvolatile memory by a software address sequence. the stk14c88-5 software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is import ant that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0fc0, initiate store cycle the software sequence is clocked with ce controlled reads. when the sixth address in the sequence is entered, the store cycle commences and the chip is di sabled. it is important that read cycles and not write cycles are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0c63, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared, and then the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is once again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. figure 4. autostore inhibit mode [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 5 of 17 data protection the stk14c88-5 protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the stk14c88-5 is in a write mode (both ce and we are low) at power up after a recall or after a store, the write is inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power up or brown out condi- tions. noise considerations the stk14c88-5 is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. hardware protect the stk14c88-5 offers hardware protection against inadvertent store operation and sram writes during low voltage condi- tions. when v cap stk14c88-5 document number: 001-51038 rev. ** page 6 of 17 best practices nvsram products have been used effectively for over 15 years. while ease of use is one of t he product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique nv pattern (for example, comp lex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard agai nst events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). the v cap value specified in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the higher inrush currents may reduce the reliability of the internal pass transistor. customers that want to use a larger v cap value to make sure there is extra store charge should discuss their v cap size selection with cypress to understand any impact on the v cap voltage level at the end of a t recall period. table 1. hardware mode selection ce we hsb a13?a0 mode io power h x h x not selected output high z standby l h h x read sram output data active [1] l l h x write sram input data active x x l x nonvolatile store output high z i cc2 [2] l h h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [1, 3, 4, 5] l h h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [1, 3, 4, 5] notes 1. i/o state assumes oe < v il . activation of nonvolatile cycles does not depend on state of oe . 2. hsb store operation occurs only if an sram write has been done sinc e the last nonvolatile cycle. after the store (if any) complete s, the part goes into standby mode, inhibiting all operations until hsb rises. 3. ce and oe low and we high for output behavior. 4. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle. 5. while there are 15 addresses on the stk14c88-5, only the lower 14 are used to control software modes. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 7 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c temperature under bias ............................. ?55 c to +125 c voltage on input relative to gnd.....................?0.5v to 7.0v voltage on input relative to vss............ ?0.6v to v cc + 0.5v voltage on dq 0-7 or hsb .......................?0.5v to vcc + 0.5v power dissipation.......................................................... 1.0w dc output current (1 output at a time, 1s duration) .... 15 ma operating range range ambient temperature v cc military -55 c to +125 c 4.5v to 5.5v dc electrical characteristics over the operating range (v cc = 4.5v to 5.5v) [6] parameter description test conditions min max unit i cc1 average v cc current t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. 85 70 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 3ma i cc3 average v cc current at t rc = 200 ns, 5v, 25c typical we > (v cc ? 0.2v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 10 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 2ma i sb1 [7] v cc standby current (standby, cycling ttl input levels) t rc = 35 ns, ce > v ih t rc = 45 ns, ce > v ih 26 23 ma ma i sb2 [7] v cc standby current ce > (v cc ? 0.2v). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. 1.5 ma i ix input leakage current v cc = max, v ss < v in < v cc -1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il -5 +5 a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma 2.4 v v ol output low voltage i out = 8 ma 0.4 v v bl logic ?0? voltage on hsb output i out = 3 ma 0.4 v v cap storage capacitor between v cap pin and vss, 6v rated. 68 f + 20% nom. 54 260 uf data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k notes 6. v cc reference levels throughout this data sheet refer to v cc if that is where the power s upply connection is made, or v cap if v cc is connected to ground. 7. ce > v ih does not produce standby current levels until any nonvolatile cycle in progress has timed out. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 8 of 17 capacitance in the following table, the capacitance parameters are listed. [8] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 5pf c out output capacitance 7pf thermal resistance in the following table, the thermal resistance parameters are listed. [8] parameter description test conditions 32-cdip 32-lcc unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd tbd c/w jc thermal resistance (junction to case) tbd tbd c/w figure 7. ac test loads ac test conditions 5.0v output 30 pf r1 963 r2 512 5.0v output 5 pf r1 963 r2 512 for tri-state specs input pulse levels .................................................... 0v to 3v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ...... .............. 1.5v note 8. these parameters are guaranteed by design and are not tested. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 9 of 17 ac switching characteristics sram read cycle parameter description 35 ns 45 ns unit min max min max cypress parameter alt t ace t elqv chip enable access time 35 45 ns t rc [9] t avav, t eleh read cycle time 35 45 ns t aa [10] t avqv address access time 35 45 ns t doe t glqv output enable to data valid 15 20 ns t oha [10] t axqx output hold after address change 5 5 ns t lzce [11] t elqx chip enable to output active 5 5 ns t hzce [11] t ehqz chip disable to output inactive 13 15 ns t lzoe [11] t glqx output enable to output active 0 0 ns t hzoe [11] t ghqz output disable to output inactive 13 15 ns t pu [8] t elicch chip enable to power active 0 0 ns t pd [8] t ehiccl chip disable to power standby 35 45 ns switching waveforms figure 8. sram read cycle 1: address controlled [9, 10] figure 9. sram read cycle 2: ce and oe controlled [9] w 5& w $$ w 2+$ $''5(66 '4'$7$287 '$7$9$/,' $''5(66 w 5& &( w $&( w /=&( w 3' w +=&( 2( w '2( w /=2( w +=2( '$7$9$/,' $&7,9( 67$1'%< w 38 '4'$7$287 ,&& notes 9. we and hsb must be high during sram read cycles. 10. device is continuously selected with ce and oe both low. 11. measured 200 mv from steady state output voltage. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 10 of 17 sram write cycle parameter description 35 ns 45 ns unit min max min max cypress parameter alt t wc t avav write cycle time 35 45 ns t pwe t wlwh, t wleh write pulse width 25 30 ns t sce t elwh, t eleh chip enable to end of write 25 30 ns t sd t dvwh, t dveh data setup to end of write 12 15 ns t hd t whdx, t ehdx data hold after end of write 0 0 ns t aw t avwh, t aveh address setup to end of write 25 30 ns t sa t avwl, t avel address setup to start of write 0 0 ns t ha t whax, t ehax address hold after end of write 0 0 ns t hzwe [11,12] t wlqz write enable to output disable 13 15 ns t lzwe [11] t whqx output active after end of write 5 5 ns switching waveforms figure 10. sram write cycle 1: we controlled [13, 14] figure 11. sram write cycle 2: ce controlled [13, 14] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 12. if we is low when ce goes low, the outputs remain in the high impedance state. 13. hsb must be high during sram write cycles. 14. ce or we must be greater than v ih during address transitions. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 11 of 17 autostore or power up recall parameter alt description stk14c88-5 unit min max t hrecall [15] t restore power up recall duration 550 s t store [16] t hlhz store cycle duration 10 ms t delay [16] t hlqz , t blqz time allowed to complete sram cycle 1 s v switch low voltage trigger level 4.0 4.5 v v reset low voltage reset level 3.6 v t vccrise v cc rise time 150 s t vsbl [13] low voltage trigger (v switch ) to hsb low 300 ns switching waveforms figure 12. autost ore/power up recall we nt 15. t hrecall starts from the time v cc rises above v switch . 16. ce and oe low and we high for output behavior. 17. hsb is asserted low for 1us when v cap drops through v switch . if an sram write has not taken place since the last nonvolatile cycle, hsb is released and no store takes place. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 12 of 17 software controlled store/recall cycle the software controlled store/recall cycle follows. [19] parameter alt description 35 ns 45 ns unit min max min max t rc [16] t avav store/recall initiation cycle time 35 45 ns t sa [18, 19] t avel address setup time 0 0 ns t cw [18, 19] t eleh clock pulse width 25 30 ns t hace [18, 19] t elax address hold time 20 20 ns t recall recall duration 20 20 s switching waveforms figure 13. ce controlled software store/recall cycle [19] t rc t rc t sa t sce t hace t store / t recall data valid data valid 6 # s s e r d d a 1 # s s e r d d a high impedance address ce oe dq (data) notes 18. the software sequence is clocked on the falling edge of ce without involving oe (double clocking aborts the sequence). 19. the six consecutive addr esses must be read in the order listed in the mode selection table. we must be high during a ll six consecutive cycles. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 13 of 17 hardware store cycle parameter alt description stk14c88-5 unit min max t dhsb [16, 20] t recover, t hhqx hardware store high to inhibit off 700 ns t phsb t hlhx hardware store pulse width 15 ns t hlbl hardware store low to store busy 300 ns switching waveforms figure 14. hardware store cycle note 20. t dhsb is only applicable after t store is complete. [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 14 of 17 ordering information speed (ns) ordering code package diagram package type operating range 35 stk14c88-5c35m 001-51694 32-pin cdip (300 mil) military STK14C88-5K35M 001-51694 32-pin cdip (300 mil) stk14c88-5l35m 51-80068 32-pin lcc (450 mil) 45 stk14c88-5c45m 001-51694 32-pin cdip (300 mil) stk14c88-5k45m 001-51694 32-pin cdip (300 mil) stk14c88-5l45m 51-80068 32-pin lcc (450mil) the above table contains final information. please contact your local cypress sales representativ e for availability of these pa rts speed: 35 - 35 ns 45 - 45 ns package: c = ceramic 32-pin 300 mil dip part numbering nomenclature stk14c88 - 5 c 35 m temperature range: m - military (-55 to 125c) k l = ceramic 32-pin llc = ceramic 32-pin 300 mil dip (solder dip finish) retention / endurance 5 = military (10 years or 10 5 cycles) [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 15 of 17 package diagram figure 15. 32-pin (300-mil) side braze dil (001-51694) 001-51694 ** [+] feedback
stk14c88-5 document number: 001-51038 rev. ** page 16 of 17 figure 16. 32-pad (450-mil) lcc (51-80068) package diagram (continued) 51-80068- ** [+] feedback
document number: 001-51038 rev. ** revised march 02, 2009 page 17 of 17 autostore and quantumtrap are registered trademarks of cypress semiconductor corporation. all products and company names mentio ned in this document may be the trademarks of their respective holders. stk14c88-5 ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: stk14c88-5 256 kbit (32k x 8) autostore nvsram document number: 001-51038 rev ecn no. orig. of change submission date description of change ** 2666844 gvch/pyrs 03/02/09 new data sheet [+] feedback

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